CoWos Packaging Engineer Job at Info Way Solutions, San Jose, CA

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  • Info Way Solutions
  • San Jose, CA

Job Description

Location - Bay Area, CA

Skills - CoWoS Packaging Engineer

Position Overview

We are seeking a skilled and motivated CoWoS Packaging Engineer to join our growing team. This role focuses on the development and optimization of Chip-on-Wafer-on-Substrate (CoWoS) packaging technology to support high-performance AI and data center applications. You will collaborate with design, process, manufacturing, and materials teams to enable seamless integration of advanced multi-die packages. If you are passionate about cutting-edge semiconductor packaging and want to help shape the future of AI infrastructure, we’d love to hear from you.

Responsibilities

  • Develop and optimize CoWoS packaging processes to improve chip performance, power, and reliability
  • Collaborate with design, test, and manufacturing teams for seamless chip-package integration
  • Drive failure analysis and yield improvements across packaging flows
  • Ensure CoWoS packaging meets thermal, mechanical, and electrical performance requirements
  • Support new product introduction (NPI), from prototyping to high-volume manufacturing
  • Work closely with foundry and OSAT partners (e.g., TSMC, ASE) on process qualification and production ramp-up

Qualifications

  • Bachelor’s or Master's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or related field
  • Minimum 15 years Hands-on experience in advanced semiconductor packaging and interconnect processes
  • Hands-on experience in advanced semiconductor packaging and interconnect processes
  • Familiarity with CoWoS, InFO, Fan-Out, and 2.5D/3D integration technologies
  • Strong understanding of thermal management, reliability testing, and signal/power integrity challenges
  • Excellent analytical and problem-solving skills with a proactive, collaborative approach
  • Experience working with TSMC and leading OSATs

Job Tags

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